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DDR3 Tri-Channel Roundup – June 2009

DDR3 Tri-Channel Roundup – June 2009

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Dissertation Proposals When Core-i7 launched in November 2008 it brought with it a new DDR3 architecture which used three channels, one more than that available on older Intel and AMD CPUs. Along with the new channel arrangement (which was managed by a controller within the CPU) was a requirement that memory operate at a maximum of 1.65v. This meant that memory manufacturers who had been using voltages as high as 1.9v on their high specification DDR3 had to rethink their practices.

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