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hUMA; AMDs Heterogeneous Unified Memory Architecture Revealed

hUMA; AMDs Heterogeneous Unified Memory Architecture Revealed

Years ago, AMD set forth on a crusade to seamlessly blend multiple functions which were normally spread throughout disparate regions of a system into one all-encompassing chip. This “system on a chip” approach wasn’t anything new but AMD has arguably been the leader in this field, often going through the process of integration long before their rival Intel.

This process started in a straightforward manner with the simple integration of a memory controller into the CPU’s die space. Subsequent iterations have gradually given birth to what we now call Accelerated Processing Units (or APUs) which have taken incorporated a reasonably powerful graphics processor into the same package as well. However, AMD isn’t stopping there. Their ultimate goal is to create what’s now called a Heterogeneous System Architecture in which all parts of the processing pipeline –be it the parallel processing capabilities of a GPU or the CPU’s serial-centric focus- communicate in harmony without any of the latency associated with multi-chip approaches.

While Trinity and its predecessor Llano took the first tentative steps towards this HSA approach, they actually featured very few architectural improvements that could be considered next generation in nature. However, the upcoming Kaveri (due in the second half of 2013) APUs will be the first leap towards the realization of AMD’s long term goals. One of their key elements will be a new Heterogeneous Unified Memory Architecture or hUMA in an effort to eliminate some of HSA’s latent bottlenecks.

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Read More/Source: Hardware Canucks 

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