Obviously with all these changes there comes a plethora of platform level alterations including the modification of the north bridge chip, or memory controller hub (MCH). This is now called the I/O Hub, or IOH.
The new Xeon’s first IOH has been called Tylersburg-36D (the code name), and is now officially named the Intel 5520 chipset. True to the definition of the name the IOH is focused on PCI Express connectivity, with one QPI link dedicated to each of the two processors and a total of 42 PCIe lanes onboard, 36 of which are PCIe Gen 2 and six Gen 1.
These lanes can be grouped into various sizes depending on the specific needs of the user and the system. Tylersburg also has a ESI port for connecting to an Intel south bridge chip, a member of the ICH9/10/R family. These chips provide SATA and USB ports as well as various levels of legacy connectivity.
Tylerburg’s dual QPI links open up the option of dual IOH chips which Intel has decided to enable for specific configurations. In a situation like this, each Tylerburg chip is linked via QPI to a different CPU and the two IOH chips are linked via QPI as well. The main/primary IOH handles various legacy I/O tasks as well as system management operations and the secondary IOH merely provides 36 additional lanes of PCIe Gen 2 connectivity for a total of 72 lanes in the system, as well as the aforementioned six Gen 1 lanes. If this all sounds double dutch to you, let me just state that this is a huge amount of connectivity and the subsequent bandwidth is massive.
The new Xeons slot into the new LGA1366 style socket that looks just like the Core I7s. There is support for 6 SATA drives.