Thanks to Mackey D for pointing me in the direction of this article @ Chip-architect.com! that talks about 4-way HyperThreading in Intel's P4 Prescott Processors!
More uOps in flight improves the performance of hyperthreaded applications
We already saw in our previous article that many buffers on Intel's Prescott's die have increased significantly in size. These larger buffers are needed to support more uOps (micro-operations) that can be in-flight in the micro architecture. The Pentium 4 can have a total of 126 instructions in-flight to allow extensive out of order processing. Hyper threading increases the need for in-flight uOps. A Pentium 4 with two threads limits the number of in-flight uOps to 63 for each thread thereby reducing the out of order capabilities and thus the performance. It now looks like that the new Prescott/Nocona will double the number of in-flight uOps to 256.
Prescott / Nocona doubles in flight uOps
Mar 25, 2003, 01:07 PM
