Source: Ars Technica
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I've covered Intel's 3D chip stacking plans in the past, but RWT has just posted a new article that goes into a ton of great detail on what 3D integration is, how it works, and what its implications are for processor performance. The article is fairly technical, and David Kanter e-mailed me to suggest that I do a sort of translation/summary for a more general audience. So for those of you who might not be as inclined to wade through either the original article or the references at the end, I've put together the following brief summary of the contents. If you're a CPU buff, you'll definitely want to check this out, because the future of microprocessors is clearly three-dimensional.