Understanding AMD's "TLB" Processor Bug

Vikingod · Dec 6, 2007, 05:39 AM

Source: DailyTech
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Much of AMD's bad luck over the last three months revolves around a nasty bug it just can't shake

Erratum, to those in the hardware or software industry, is a nice way of saying "we missed a test case" during development and design.

Yesterday, The Tech Report confirmed AMD's iteration of Intel's F00F bug. The bug, which has been documented since at least early November, can cause a deadlock during recursive or nested cache writes.

How does the TLB erratum occur? All AMD quad-core processors utilize a shared L3 cache. In instances where the software uses nested memory pages, this processor will experience a race condition.

Judas · Dec 6, 2007, 05:51 AM

holy crap... that's HUGE!......

Dec 6, 2007, 05:39 AM	#1
Vikingod Int'l Fish Liaison Join Date: Jul 2004 Location: By the light of lamp I sit and type... Posts: 16,187 Rep Power: 109 System Specs	Understanding AMD's "TLB" Processor Bug Source: DailyTech ______________ Much of AMD's bad luck over the last three months revolves around a nasty bug it just can't shake Erratum, to those in the hardware or software industry, is a nice way of saying "we missed a test case" during development and design. Yesterday, The Tech Report confirmed AMD's iteration of Intel's F00F bug. The bug, which has been documented since at least early November, can cause a deadlock during recursive or nested cache writes. How does the TLB erratum occur? All AMD quad-core processors utilize a shared L3 cache. In instances where the software uses nested memory pages, this processor will experience a race condition. __________________ *How You Can Help DriverHeaven By Using Digg*