AMD comments on quad-core erratum and shipments

Vikingod · Dec 7, 2007, 01:50 PM

Source: DigiTimes
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In response to recent reports of the existence of an erratum involving the L3 cache of AMD's new Opteron (Barcelona) and Phenom processors and that shipments of the parts have been delayed, AMD clarified that the company sent notice to clients about the erratum and offered a BIOS fix prior to November 19 and that the company is shipping Phenom parts to channel, system builders and OEM customers.

The company also noted that currently, quad-core Opteron processors are only being shipped to specific end-users for validation of stability and robustness of the solution and that the quad-core Opteron CPUs available in the first quarter of 2008 will not have the erratum issue.

AMD's Barcelona and Phenom quad-core processors were reported to have an erratum issue involving the translation lookaside buffer (TLB) logic of the L3 cache, according to a recent Tech Report article, while reports have been circulating that shipments of the Opteron processors have been delayed.

Dec 7, 2007, 01:50 PM	#1
Vikingod Int'l Fish Liaison Join Date: Jul 2004 Location: By the light of lamp I sit and type... Posts: 16,197 Rep Power: 112 System Specs	AMD comments on quad-core erratum and shipments Source: DigiTimes ___________ In response to recent reports of the existence of an erratum involving the L3 cache of AMD's new Opteron (Barcelona) and Phenom processors and that shipments of the parts have been delayed, AMD clarified that the company sent notice to clients about the erratum and offered a BIOS fix prior to November 19 and that the company is shipping Phenom parts to channel, system builders and OEM customers. The company also noted that currently, quad-core Opteron processors are only being shipped to specific end-users for validation of stability and robustness of the solution and that the quad-core Opteron CPUs available in the first quarter of 2008 will not have the erratum issue. AMD's Barcelona and Phenom quad-core processors were reported to have an erratum issue involving the translation lookaside buffer (TLB) logic of the L3 cache, according to a recent Tech Report article, while reports have been circulating that shipments of the Opteron processors have been delayed.